1. Field of the Invention
This invention relates to an input/output (I/O) circuit, and more particularly to using a feedback circuit in the I/O circuit to increase the I/O voltage tolerance.
2. Description of Related Art
An integrated circuit (IC) device includes a number of electronic elements such as resistors, capacitors, transistors and switches, which are made of semiconductor materials, such as silicon or gallium arsenide, and are fabricated together on a semiconductor substrate by fabricating technologies, such as photolithography, etching, chemical vapor deposition (CVD) and so on. The IC device including many electronic elements, therefore, appears in a size about 1.about.2 cm.sup.2 with thickness about 1 mm.
Basically, any IC device is composed of a number of conductors, semiconductors and dielectrics, which are orderly formed together according to the circuit design. For example, a metal oxide semiconductor (MOS) device is composed of a metal layer, an oxide layer and a semiconductor layer, which are sequentially formed. When a bias is applied on the MOS device between the metal layer and the semiconductor layer, certain charges are stored on an interface, or called PN junction, between the oxide layer and the semiconductor layer. The MOS device behaves like a capacitor. If the applied bias keeps on increasing, the charge density is accordingly brought up and then reaches a critical density, which is high enough to invert the type of the semiconductor, such as a P-type semiconductor turns to an N-type semiconductor. This phenomenon is called inversion. A strong inversion can happen if the applied bias is higher than a threshold voltage. When a MOS device stays on the strong inversion situation, if there are another two side MOS devices with different semiconductor type separately located at the sides of the MOS device, these three MOS devices are then coupled together through an inversion layer of the MOS device. The inversion layer, which has the same semiconductor type as the side MOS devices, is resulted from the strong inversion to change the semiconductor type.
Thus, if the applied bias is higher than the threshold voltage, the IC device can normally work. If the applied bias is too high, which has cross over a breakdown voltage of the IC device, since load of the IC device is too high, the PN junction and the gate oxide of a MOS transistor can be damaged. A phenomenon of leakage current therefore can happen and, even more serious, the IC device could be burnt down.
For example, in an IC device using two voltage sources of 3.3 V and 5 V, if the IC device has one bus for common uses, the part of the IC device using the bias of 3.3 V should sense a stress induced by the bias of 5 V and get a result of damages on the output PN junction and the gate oxide. One conventional solution for this problem is forming a dual gate oxide instead of a single gate oxide to increase the breakdown voltage and further prolong the lifetime, which is the happening time of a time-dependent dielectric breakdown (TDDB). The TDDB is related to the IC reliability. However, although the dual gate oxide structure can solve the above problem, the fabricating costs are about 15% higher than the fabricating costs for a single gate oxide structure.
Another solution is done through a circuitry technology. FIG. 1 is a schematic conventional I/O circuit, which has been disclosed by AT&T in an U.S. Pat. No. 5,381,062, "MULTIVOLTAGE COMPATIABLE BIDIRECTIONAL BUFFER".
In FIG. 1, an output pad 10 is coupled to an output of a 5 V IC device 9. When the 5 V IC device 9 receives a driving voltage of 5 V from a 5 V-voltage source 8, an output the output pad 10 is driven by the 5 V IC device 9 and then provides a 5 V bias to the circuit. The circuit includes two PMOS transistors 11, 12 connected serially and two NMOS transistors 13, 14 connected serially. The gate of the PMOS transistor 11 is, for example, coupled to a driver output (not shown) through a node 15 and the gate of the NMOS transistor 14 is, for example, coupled to a driver output (not shown) through a node 16. The nodes 15, 16 are used to control the output levels to be either "high" or "low", which determine the "ON" or "OFF" statuses of the PMOS transistor 11 and the NMOS transistor 14. When the circuit is at a sourcing mode, the 5 V bias from the output pad 10 goes through the PMOS transistors 11, 12. When the circuit is at a sinking mode, the 5 V bias from the output pad 10 goes through the NMOS transistors 13, 14. The circuit shown in FIG. 1 can effectively solve the problems of the reliability of the oxide layer and the leakage current of the PMOS transistors 11,12. In other word, the part of IC powered by 3.3 V is not affected by the 5 V bias. Although the problems as described above are solved, the output impedance turns to higher because a necessary rout through the PMOS transistors 11, 12 for the sourcing mode and a necessary rout through the NMOS transistors 13, 14 for the sinking mode. This decreases the transmission speed of voltage source.
FIG. 2 is a schematic block diagram of another conventional I/O circuit, which has been disclosed by TSMC at a U.S. Pat. No. 5,546,019, "CMOS I/O CIRCUIT WITH 3.3 V OUTPUT AND TOLERANCE OF 5 V INPUT".
In FIG. 2, the I/O circuit includes an output pad 20, a pull-up circuit 21, a PMOS transistor 22, two NMOS transistors 23, 24, and a control circuit 25. According the I/O circuit in FIG. 2, a problem of the forward bias on the PN junction of the PMOS transistor 22 can be solved, and by a full swing situation can be achieved by using the pull-up circuit 21. The control circuit 25 is used to control the output at "low" level or "high", which determine the states of the PMOS transistor 21 and the NMOS transistor 23,24 to be either "ON" or "OFF". When the NMOS transistor 24 is "OFF", the NMOS transistor 24 is in a high impedance status and its gate oxide is loaded by 5 V from the output pad 20. So, the oxide layer can potentially be damaged. This gives a poor reliability of the oxide layer.
As described above, the conventional I/O circuits have drawbacks as follows:
1. When an IC needs two different biases, which are supplied from a single bus, even though a dual gate oxide is used to replace a single gate oxide for increasing the breakdown voltage, the fabricating costs is therefore increased. PA1 2. When the I/O circuit is at the sourcing mode or the sinking mode, it needs to go through two PMOS transistors 11, 12 connected serially or two NMOS transistors 13, 14 connected serially, respectively. In this case, the output impedance is increased such that the transmission speed of voltage source is decreased. PA1 3. When the NMOS transistor 24 is "OFF", the NMOS transistor 24 is in a high impedance status and its gate oxide is loaded by 5 V from the output pad 20. So, the gate oxide can potentially be damaged. This gives a poor reliability of the gate oxide.